[Misunderstanding and Advancement of Using Vivado]Application of Tcl in Vivado
Compared with the previous generation ISE, Xilinx’s next-generation design suite Vivado has significantly improved in many aspects such as running speed, algorithm optimization and functional integration. But for beginners, the introduction of the new constraint language XDC and the scripting language Tcl has become the biggest obstacle to quickly mastering Vivado usage skills, so that today, more than two years later, many users still lack the confidence to upgrade to Vivado.
This article introduces the basic application of Tcl in Vivado, hoping to play a role as a guide to guide users to quickly master relevant skills in a short period of time, so as to better utilize the advantages of Vivado in FPGA design.
Background introduction and basic grammar of Tcl
Tcl (pronounced tickle) was born at the University of California, Berkeley in the 1980s. As a simple, efficient and portable scripting language, it has been widely used in almost all EDA tools. The biggest feature of Tcl is that its syntax format is extremely simple or even rigid, using pure [命令 选项 参数] Form, is a veritable “tool command language” (that is, Tcl’s full name Tool Command Language).
In fact, Tcl can be very powerful, and the programs written with it can be very complex, but to use it in Vivado or most other EDA tools, you only need to master the most basic parts.
Note: In the following example, % represents the command prompt of Tcl. After executing the carriage return, Tcl will output the command execution result on the next line. // followed by a comment by the author, not part of the example.
set variable
Printing is mainly performed through the puts statement, and with special symbols, the final output content is directly determined.
file I/O
It can be seen that Tcl’s operations on files are also carried out by setting variables, changing attributes and printing commands. In the above example of writing a file, two lines of text are written in the my_file.txt file through the puts command, which are “Hello World!” and the value of the myVar variable, and then the content of the same file is read in the file read operation.
Control flow and loop commands
Commands used to control flow and loops in Tcl are similar to those in C and other high-level languages, including if, while, for, and foreach, among others.
For specific use, please refer to the following examples:
subroutine/procedure
Subroutines in Tcl are also called procedures (Procedures). Tcl enhances its built-in command capabilities by creating new procedures and provides stronger extensibility. Specific to the use of Vivado, users can often extend or personalize the use of Vivado by creating subroutines/processes.
some special symbols
The basic syntax of Tcl language is relatively simple, but it still requires daily practice to master it. There are a lot of relevant materials on the Xilinx website. Here are two Tcl-related documents, UG835 and UG894, which I hope will help you learn Vivado and Tcl.
Locating target with Tcl in Vivado
The most basic scenario of using Tcl in Vivado is to traverse, search and locate the target on the netlist, which is also the basis for constraining the target on the netlist. To master these, you first need to understand Vivado’s classification of targets.
Definition and positioning of goals
As shown in the figure above, the I/Os at the top level of the design are called ports, and the other low-level modules or component ports on the gate-level netlist are called pins. The modules at all levels including the top layer, blackbox and gate-level components are called cells. The connection is called nets, plus the clocks defined in XDC, a total of five categories of objects in the netlist file are defined in Vivado. To select these five types of targets, you need to use the corresponding get_* commands, such as get_pins and so on.
get_ports
Ports only refer to top-level ports, so the use of get_ports is relatively simple, and can be used together with the wildcard “*” and commands that process lists in the Tcl language. As follows,
get_cells/get_nets
Unlike ports, which only refer to top-level ports, it is relatively complicated to locate cells and nets. First, you need to face the problem of hierarchy. Here is a big background to be clear: Tcl/XDC in Vivado searches for objects in the netlist hierarchically, that is, only one specified level current_instance is searched at a time, and the default value is the top level.
The design shown in the following figure is an example. To search for all cells in the A (excluding a1, a2) level and nets with nt in the name, there are two methods:
If you want to change the search level to A+B+b1, you can write a loop, use current_instance to point the search level to A, B and b1 one by one, and then combine the searched cells or nets into a list output.
To change the search hierarchy to the current hierarchy and all sub-hierarchies below it, use -hierarchical (shortened to -hier in Tcl).
When using -hierarchical, you need to pay special attention, that is, the following search conditions only refer to the name of the target object, and cannot contain “/” representing the hierarchy. The writing method listed below is a common misunderstanding, and cannot be used to search all cells in A and its sub-levels.
get_pins
pins have a unique form of existence in the Vivado database, namely
relationship between goals
When Tcl searches for objects in the netlist, in addition to the above-mentioned direct search method based on name conditions, it can also use the relationship between objects and use -of_objects (can be abbreviated as -of in Tcl) to indirectly search for specific objects. The relationship between the five types of goals defined in Vivado is shown in the left figure below.
The design shown on the right above is an example,
The image below is a more complex example involving searching across hierarchies. It can be seen that when get_pins, you need to add -leaf to accurately locate the port q of the gate-level component (or blackbox). In addition, in actual operation, when using get_nets and get_pins, you need to add other conditions (-filter) depending on the situation to accurately find the cells (i2) in the following example.
Advanced Find Features
When using the get_* command to find the target in the netlist, in addition to the direct condition of the name, it is often necessary to supplement other more complex condition judgments, which requires the use of advanced search functions: -filter combined with various relationships supported by Tcl and logical operators (==, !=, =~, !~, <=, >=, >, <, &&, ||) or even regular expressions.
-filter is also often used when creating subprograms. For example, the following subprogram/procedure of get_p can be used to return the direction attribute of the specified pin, telling the user whether it is an input pin or an output pin. It should be pointed out that { } is usually used after -filter, but in this case, you need to do variable substitution for $direction, you must use ” ” instead as shown below
Extended Application of Tcl in Vivado
The application of Tcl in Vivado is far more than those listed above. Other commonly used functions include using pre-written Tcl scripts to run the design and implementation process, creating advanced constraints (XDC does not support advanced Tcl syntax such as loops), and implementing complex personalization. design process, etc. The powerful extensibility brought by Tcl determines that it has incomparable advantages in graphical interface in version control, design automation process and so on.
In the process of continuous development and updating of Vivado, there are many new functions, including ECO, PR, HD Flow, etc., which are supported from the Tcl script method, and then gradually implemented in the graphical interface. This also explains why both high-end FPGA users and proficient Vivado users prefer Tcl scripts.
Due to space limitations, it cannot be expanded one by one. For the extended application of the above Tcl in Vivado, please pay attention to more technical articles on Xilinx official website and Chinese forum.
Ally Zhou 2014-9-12 at Xilinx Shanghai Office
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