PCB design signal integrity is good, all due to these problems found early
“Signal Integrity (Signal Integrity, SI) refers to the quality of the signal on the signal line, that is, the ability of the signal to respond with the correct timing and voltage in the circuit. If the signal in the circuit can reach the receiver with the required timing, duration, and voltage amplitude, it can be determined that the circuit has good signal integrity. Conversely, when the signal cannot respond normally, a signal integrity problem occurs.
Signal Integrity (Signal Integrity, SI) refers to the quality of the signal on the signal line, that is, the ability of the signal to respond with the correct timing and voltage in the circuit. If the signal in the circuit can reach the receiver with the required timing, duration, and voltage amplitude, it can be determined that the circuit has good signal integrity. Conversely, when the signal cannot respond normally, a signal integrity problem occurs.
With the use of high-speed devices and more and more high-speed digital system designs, the system data rate, clock rate, and circuit density are constantly increasing. In this design, the system has fast slope transients and high operating frequencies. Cables, interconnects, printed boards (PCBs), and silicon chips will exhibit completely different behaviors from low-speed designs, that is, signal integrity problems occur. Signal integrity problems can cause or directly cause signal distortion, timing errors, incorrect data, address, control lines, and system errors, and even crash the system. This has become a very noteworthy problem in the design of high-speed products. This article first introduces the problem of PCB signal integrity, then explains the steps of PCB signal integrity, and finally introduces how to ensure the signal integrity of PCB design.
PCB signal integrity issues include
PCB signal integrity problems mainly include signal reflection, crosstalk, signal delay, and timing errors.
1. Reflection: When the signal is transmitted on the transmission line, when the characteristic impedance of the transmission line on the high-speed PCB does not match the source impedance or load impedance of the signal, the signal will reflect, causing the signal waveform to overshoot and undershoot. The ringing phenomenon. Overshoot (Overs hoot) refers to the first peak (or valley) of a signal transition, which is the effect of extra voltage above the power supply level or below the reference ground level; undershoot (Unders hoot) refers to The next valley (or peak) of the signal transition. Excessive overshoot voltage often impacts for a long time to cause damage to the device, undershoot reduces the noise margin, and ringing increases the time required for signal stabilization, thereby affecting system timing.
2. Crosstalk: In PCB, crosstalk refers to the undesired noise interference caused by electromagnetic energy to adjacent transmission lines through mutual capacitance and mutual inductance coupling when the signal propagates on the transmission line. It is the electromagnetic field caused by different structures. Produced by the interaction in the same area. Mutual capacitance induces coupling current, which is called capacitive crosstalk; and mutual inductance induces coupling voltage, which is called inductive crosstalk. On the PCB, crosstalk is related to trace length, signal line spacing, and the condition of the reference ground plane.
3. Signal delay and timing error: The signal is transmitted on the PCB wire at a limited speed, and the signal is sent from the driving end to the receiving end, during which there is a transmission delay. Excessive signal delay or signal delay mismatch may cause timing errors and confusion of logic device functions.
High-speed digital system design analysis based on signal integrity analysis can not only effectively improve product performance, but also shorten product development cycles and reduce development costs. With the development of digital systems in the direction of high speed and high density, it is very urgent and necessary to master this design tool. In the continuous improvement and improvement of the signal integrity analysis model and calculation analysis algorithm, the digital system design method using signal integrity for computer design and analysis will be widely and comprehensively applied.
PCB signal integrity steps
1. Preparation before design
Before the design begins, we must first think and determine the design strategy, so as to guide work such as the selection of components, process selection and circuit board production cost control. As far as SI is concerned, it is necessary to conduct research in advance to form planning or design guidelines to ensure that the design results do not have obvious SI problems, crosstalk or timing problems.
2. The stacking of circuit boards
Some project teams have great autonomy in determining the number of PCB layers, while others do not. Therefore, it is important to understand where you are.
Other important questions include: What are the expected manufacturing tolerances? What is the expected insulation constant on the circuit board? What is the allowable error of line width and spacing? What is the allowable error of the thickness and spacing of the ground layer and signal layer? All this information can be used in the pre-wiring phase.
Based on the above data, you can choose to cascade. Note that almost every PCB inserted into other circuit boards or backplanes has thickness requirements, and most circuit board manufacturers have fixed thickness requirements for the different types of layers they can manufacture, which will greatly restrict the number of final stacks . You may want to work closely with the manufacturer to define the number of cascades. Impedance control tools should be used to generate target impedance ranges for different layers, and the manufacturing tolerances provided by the manufacturer and the influence of adjacent wiring must be taken into consideration.
In the ideal case of signal integrity, all high-speed nodes should be routed in an impedance controlled inner layer (such as a stripline). To optimize SI and maintain circuit board decoupling, the ground plane/power plane should be placed in pairs as much as possible. If there can only be a pair of ground plane/power plane, you have only one pair. If there is no power layer at all, by definition you may encounter SI problems. You may also encounter situations where it is difficult to simulate or simulate the performance of the circuit board before the return path of the signal is defined.
3. Crosstalk and impedance control
Coupling from adjacent signal lines will cause crosstalk and change the impedance of the signal line. The coupling analysis of adjacent parallel signal lines may determine the “safe” or expected spacing (or parallel wiring length) between signal lines or between various signal lines. For example, if you want to limit the crosstalk from clock to data signal node to less than 100mV, but keep the signal traces parallel, you can use calculations or simulations to find the minimum allowable spacing between signals on any given wiring layer. At the same time, if the design contains nodes with important impedances (or clocks or dedicated high-speed memory architectures), you must place the wiring on one layer (or several layers) to get the desired impedance.
4. Important high-speed nodes
Delay and time skew are key factors that must be considered in clock routing. Because of the strict timing requirements, such nodes usually must use termination devices to achieve the best SI quality. These nodes should be determined in advance, and the time required to adjust component placement and wiring should be planned in order to adjust the signal integrity design indicators.
5. Technology selection
Different drive technologies are suitable for different tasks. Is the signal point-to-point or point-to-multiple tapped? Is the signal output from the circuit board or stay on the same circuit board? What is the allowable time delay and noise margin? As a general rule of signal integrity design, the slower the conversion speed, the better the signal integrity. There is no reason why a 50MHZ clock uses a 500PS rise time. A 2-3NS slew rate control device must be fast enough to ensure the quality of SI and help solve problems such as synchronous output switching (SSO) and electromagnetic compatibility (EMC).
In the new FPGA programmable technology or user-defined ASIC, the superiority of the drive technology can be found. With these custom (or semi-custom) devices, you have a lot of leeway to choose drive amplitude and speed. At the beginning of the design, meet the FPGA (or ASIC) design time requirements and determine the appropriate output selection, if possible, including pin selection.
In this design stage, a suitable simulation model must be obtained from the IC supplier. In order to effectively cover the SI simulation, you will need a SI simulation program and the corresponding simulation model (probably an IBIS model).
Finally, in the pre-wiring and wiring stages, you should establish a series of design guidelines, which include: target layer impedance, wiring spacing, preferred device technology, important node topology, and termination planning.
6. Pre-wiring stage
The basic process of pre-wiring SI planning is to first define the input parameter range (drive amplitude, impedance, tracking speed) and possible topology range (minimum/maximum length, short-line length, etc.), and then run each possible simulation combination to analyze timing and SI simulation results, and finally found an acceptable range of values.
Next, the working range is explained as the wiring constraint condition of PCB wiring. Different software tools can be used to perform this type of “cleaning” preparation, and the wiring program can automatically handle this type of wiring constraint. For most users, timing information is actually more important than SI results. The results of interconnection simulation can change the wiring to adjust the timing of the signal path.
In other applications, this process can be used to determine the layout of pins or devices that are not compatible with the system timing pointer. At this point, it is possible to completely determine the nodes that need to be wired manually or that do not need to be terminated. For programmable devices and ASICs, the choice of output drive can also be adjusted at this time in order to improve the SI design or avoid the use of discrete termination devices.
7. SI simulation after wiring
Generally speaking, it is difficult for SI design guidelines to ensure that there will be no SI or timing problems after the actual wiring is completed. Even if the design is carried out under the guidance of the guidelines, unless you can continue to automatically check the design, otherwise, there is no guarantee that the design will fully comply with the guidelines, so problems will inevitably occur. The SI simulation check after wiring will allow to break (or change) the design rules in a planned way, but this is only necessary for cost considerations or strict wiring requirements.
8. Post-manufacturing stage
The above measures can be taken to ensure the quality of the SI design of the circuit board. After the circuit board is assembled, it is still necessary to place the circuit board on the test platform, use an oscilloscope or TDR (time domain reflectometer) to measure, and compare the real circuit board and simulation expectations Compare the results. These measurement data can help you improve the model and manufacturing parameters so that you can make better (less constrained) decisions in the next pre-design investigation.
9. Choice of model
There are many articles on model selection, and engineers performing static timing verification may have noticed that although all the data can be obtained from the device data sheet, it is still very difficult to build a model. The SI simulation model is just the opposite. The model is easy to build, but the model data is difficult to obtain. In essence, the only reliable source of SI model data is the IC supplier, who must maintain a tacit cooperation with the design engineer. The IBIS model standard provides a consistent data carrier, but the establishment of the IBIS model and its quality assurance are costly. IC suppliers still need to drive market demand for this investment, and the circuit board manufacturer may be the only buyer. market.
PCB design method to ensure signal integrity
By summarizing the factors that affect signal integrity, the PCB design process can better ensure signal integrity, which can be considered from the following aspects.
(1) Considerations in circuit design. Including controlling the number of synchronous switching outputs, controlling the maximum edge rate (dI/dt and dV/dt) of each unit to obtain the lowest and acceptable edge rate; selecting differential signals for high output functional blocks (such as clock drivers); in the transmission line Passive components (such as resistors, capacitors, etc.) are connected to the upper end to achieve impedance matching between the transmission line and the load.
(2) Minimize the trace length of parallel wiring.
(3) The components should be placed far away from the I/O interconnection interface and other areas susceptible to interference and coupling, and the spacing between components should be minimized.
(4) Shorten the distance between the signal trace and the reference plane.
(5) Reduce trace impedance and signal drive level.
(6) Terminal matching. Terminal matching circuit or matching components can be added.
(7) Avoid wiring parallel to each other, provide sufficient wiring spacing between wiring, and reduce inductive coupling.