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Siemens mPower Addresses Power Integrity Analysis Challenges in the Analog Hybrid Era

Siemens mPower Addresses Power Integrity Analysis Challenges in the Analog Hybrid Era

Today, as the chip capabilities become more and more powerful, the application scope of analog and digital hybrid chips and sensors is also expanding. According to Semico Research, in the technology node range of 5nm to 28nm, the number of analog modules is growing at a compound annual growth rate of 10-15%.

Today, as the chip capabilities become more and more powerful, the application scope of analog and digital hybrid chips and sensors is also expanding. According to Semico Research, in the technology node range of 5nm to 28nm, the number of analog modules is growing at a compound annual growth rate of 10-15%.

Whether battery-powered or wire-powered, low power consumption can bring tangible, practical benefits, including higher power density, longer standby times, and more stable and reliable execution efficiency. For this reason, it is necessary to conduct a comprehensive analysis and evaluation of power management during chip design.

Challenges of Large-Scale Power Integrity Analysis

Joseph Davis, senior director of product management for Calibre interfaces and mPower’s power integrity analysis tool, Siemens digital industry software, said: “Power analysis not only needs to meet the development of digital technology, but also needs to take into account the intricate sensor and other digital-analog hybrid technology. “

Power integrity is a critical step in both chip design and operation. In order to design a product that meets the goals in terms of power consumption, performance, reliability, etc., a comprehensive evaluation of power integrity is required. However, as sensors, RF, and power management grow in more and more chips, EDA tools have struggled to handle such complex power analysis. At present, designers need to use manual analysis, but the time cost and capital cost of doing so are huge.

Davis explained in detail that today’s tools cannot directly simulate large netlists, which means that it is usually limited to transistor scales of 1-2 million gates. Beyond this scale, analog developers need to block, interblock or chip in a similar way to digital. Level analysis can only be done manually and is not precise enough. For digital design, the existing power analysis scheme is not highly related to the silicon physical layer, which is easy to cause risks. At the same time, there is also a lack of integration of analog-digital hybrid solutions.

In addition, unfriendly interfaces and difficult access to PDK have become barriers that limit EM/IR analysis.

Therefore, the industry needs more efficient EM/IR analysis tools, with higher-level analysis functions, and a complete analog-digital hybrid solution provided by a single supplier, so that it is possible to accelerate the chip development process.

Introduction to EM and IR

EM (electromigration) is defined as the movement of metal atoms in IC interconnects caused by the flow of electrons at high current densities. Essentially, this is saying that when a large amount of current is passed through a small area of ​​metal, electrons collide with metal atoms. When this happens, momentum will be transferred from the electron to the atom.

This transfer causes the metal atoms to deviate from their original positions and move in the direction of the current flow. Over time, this movement of atoms creates holes or deposits of metal atoms that will eventually lead to open or short circuits, respectively.

With the development of ICs, EM has become an important power integrity issue. Because EM is directly derived from the current density (current per area). As technology nodes shrink, so does the cross-sectional area of ​​the metal interconnects used. But at the same time, as IC processing performance improves, more current is required.

Ultimately, with a significant increase in current density, resulting in short/open circuits due to EM in the power supply network, affecting power integrity.

IR drop analysis is another issue, as IC scaling leads to smaller cross-sectional areas of interconnects, and increasing resistance due to the parasitic resistance of interconnects being inversely proportional to their cross-sectional area. As the IC current increases, the IR drop across its power supply network increases significantly. These unnecessary losses can cause power integrity problems because the power delivered to the transistor itself will be less than the power output from the power supply.

mPower Advantage

Responding to the growing market demand for emerging analog and digital power integrity solutions, Siemens Digital Industries Software announces mPower™ power integrity software, the industry’s first and only Signal IC Design provides a nearly infinitely scalable solution for IC power integrity verification, enabling comprehensive power, electromigration (EM), and voltage drop (IR) analysis for even the largest IC designs.

Siemens mPower Addresses Power Integrity Analysis Challenges in the Analog Hybrid Era

Traditional analysis methods require manual analysis when the number of simulated transistors exceeds 10,000 gates, while mPower’s dynamic analysis method can support networks ranging from the smallest to 1 billion gates.

mPower software is not only suitable for all versions of 2D design and 2.5/3D IC implementation of any scale, but also can be easily integrated into existing design flows; with the help of mPower, IC designers can quickly and fully validate their designs Whether power-related design goals are being met, this capability can help IC customers improve product quality, enhance reliability, and speed time-to-market.

mPower provides analog IC designers with an innovative dynamic solution to perform highly accurate, analog-based EM/IR analysis on large modules and chips, replacing coarse static analysis and SPICE simulations of selected networks.

The analog simulation cannot be simplified according to the digital technology of 0 and 1, so nonlinear Spice analysis is required, which consumes a lot of system resources. The mPower engine is optimized and supports parallel processing of heterogeneous networks, which means that only a small amount of memory can be executed.

For PDK tools, Siemens’ extensive Foundry partnership also makes it convenient for customers to provide PDK and EM rules and other materials.

mPower provides a simplified GUI, developers can get started quickly, and improved after analysis through Calibre RVE.

mPower is widely recognized by customers

According to Davis, many customers around the world have chosen the mPower tool for power integrity verification. Including MaxLinear’s 5nm chip, Efinix’s FPGA, Esperanto’s more than 1000-core RISC-V 7nm high-performance processor, and ON semiconductor‘s sensor array digital-analog hybrid chip.

Dr. Paolo Miliozzi, Vice President of SoC Design and Technology at MaxLinear, said: “With the help of Siemens’ mPower solution that has helped us do things that were previously impossible, we can now confidently tape out large analog circuits. Evaluate EM/IR.”

Darren Jones, VP of VLSI at Esperanto, said: “Before using mPower, we could not perform a single-shot full-chip EM/IR analysis on a 64-bit RISC-V AI chip with more than 1000 cores. With mPower, we only need to It takes very few resources to run a 24 billion transistor 7nm AI chip on a server farm with better turnaround times than we had previously expected.”

Siemens mPower Addresses Power Integrity Analysis Challenges in the Analog Hybrid Era

mPower Power Integrity Analysis enables UPMEM designers to perform power optimization during floorplanning, resulting in a 10x improvement in IR effects.

Davis said that Siemens’ transistor and gate-level simulation modeling can fully meet all the needs of different types of customers, different processes, and different products. Of course, the biggest advantage is reflected in large-scale simulation design.

The mPower Power Integrity solution complements Siemens’ Electronic Physical Signoff (Signoff) suite to comprehensively address power, performance and reliability analysis, which also includes Calibre PERC software, PowerPro software, HyperLynx software and the Analog FastSPICE platform , designers can now design using the full Siemens Power Integrity Design Flow.

Joe Sawicki, executive vice president IC/EDA at Siemens, said: “Design houses must perform module and full-chip EM/IR analysis to confirm that the grid can supply the necessary current to equipment without premature failure of wires. Using Siemens’ innovative The mPower solution gives designers fast and scalable dynamic analysis capabilities for analog, digital and mixed-signal layouts of any size, with silicon-proven accuracy and fast turnaround times for the largest digital chips .”

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