Electronic
The truth revealed: what consumes all the DB?

The truth revealed: what consumes all the DB?

The signal generator is set to output a CW tone at a specific power, and according to my math equation, the ADC produces a C1 dBFS signal. However, I see a C15 dBFS signal! Who consumes all my dB?

The signal generator is set to output a CW tone at a specific power, and according to my math equation, the ADC produces a C1 dBFS signal. However, I see a C15 dBFS signal! Who consumes all my dB?

Many times ADCs (analog-to-digital converters) have rated performance at C1 dBFS. Some data sheets give distortion 0.5 dB below full scale. Whether it is 1 dB or 0.5 dB below full scale, this prevents signal clipping if the ADC input is run at full scale (0 dBFS). Benchtop RF signal generators typically output signals in dBm. To achieve C1 dBFS over the 1.7 V pp full-scale ADC range, the signal level needs only 7.6 dBm (based on a 50 Ω reference impedance). In doing so, though, the ADC’s single-tone FFT output showed C6.7 dBFS. What consumes all the dB?

The obvious answer is the ADC part. It is the front-end network of the ADC.

Let’s take a closer look at the default front-end network used for the ADC AD9680.

The truth revealed: what consumes all the DB?
Figure 1. Default Front End Network for AD9680 Evaluation Board

Converting single-ended to differential mode can be accomplished with a wideband balun BAL-0006SMG. A quick look at the BAL-0006SMG data sheet shows that it has 6 dB insertion loss. The matching network (Rs and RSH) following the balun adds another 6 dB. The matching network needs to provide broadband matching to the balun output. The series resistor in front of the ADC (RkB) exhibits a small insertion loss. This resistor improves third harmonic performance by reducing the kickback from the ADC sample stage to the hold stage.

So let’s overcome the related ADC challenges to understand the power required by the signal generator to obtain a C1 dBFS ADC signal. The 50 Ω reference resistor is used in the following mathematical equations. For the default full-scale level of 1.7 V pp, the C1 dBFS signal is 1.515 V pp. Since the 10 Ω resistor losses are quite small, we can assume that the loss voltage is the termination network voltage. The balun termination has 6 dB loss, so each side of the balun swings about twice as much as 1.515 V. This results in a single-ended input of about 3.03 V pp. Therefore, the signal generator must provide a signal corresponding to about 3.03 V pp or 14 dBm. Note that this does not include the insertion loss of the bandpass filter or the connector cable. So, look at Figure 1 again, this time we get Figure 2 with some annotations.

The truth revealed: what consumes all the DB?
Figure 2. Front-end network with integrated bandpass filter and signal generator

Back to our question again, the premise that the power required to get a -1 dBFS ADC signal is 7.6 dBm is correct if there is no interference next to the signal generator in front of the ADC. Barrons may need to be considered. There are now other factors (broadband baluns, matching networks, kickback control, etc.) that affect insertion loss, resulting in an attenuated signal at -6.7 dBFS. So you can safely say “my front end is consuming all the dB”. As you can see, mathematical equations are never wrong.

Refer to the following formulas:

The truth revealed: what consumes all the DB?

where VIN is the input voltage and VFS is the full-scale voltage

The truth revealed: what consumes all the DB?

where Vrms is the rms voltage and Vpp is the peak-to-peak voltage

The truth revealed: what consumes all the DB?

where PdBm is the signal generator power in dBm, Vrms is the rms voltage, R is the system impedance (50 Ω in this example), and P0 is 1 mW.

AD9680

• JESD204B (subclass 1) encoded serial digital output
• Total power consumption per channel at 1 GSPS: 1.65 W (default setting)
• SFDR = 85 dBFS (340 MHz), 80 dBFS (1 GHz)
• SNR = 65.3 dBFS (340 MHz, AIN = −1.0 dBFS); 60.5 dBFS (1 GHz, AIN = -1.0 dBFS)
• ENOB = 10.8 bits (10 MHz)
• DNL = ±0.5 LSB
• INL = ±2.5 LSB
• Noise Density = -154 dBFS/Hz (1 GSPS)
• DC power: 1.25 V, 2.5 V and 3.3 V
• No missing codes
• ADC internal reference
• Flexible input range
• AD9680-1000: 1.46 V pp to 1.94 V pp (1.70 V pp nominal)
• AD9680-500: 1.46 V pp to 2.06 V pp (2.06 V pp nominal)
• Programmable termination impedance
• 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
• 2 GHz available analog input full power bandwidth
• 95 dB channel isolation/crosstalk
• Amplitude detection bit support for efficient AGC
• 2 integrated wideband digital processors per channel
• 12-bit NCO, up to 4 cascaded half-band filters
• Differential clock input
• Integer clock divider value: 1, 2, 4 or 8
• Flexible JESD204B channel configuration
• Small signal perturbations

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