Thoroughly clarify the main parameters and test plan of high-speed ADC
With the continuous improvement of digital signal processing technology, digital circuit operating speed and system sensitivity, higher requirements are put forward for high-speed and high-precision ADC indicators. For example, in application fields such as mobile communication and image acquisition, on the one hand, the ADC is required to have a high sampling rate to collect high-bandwidth input signals, and on the other hand, it must have a high number of bits to distinguish subtle changes. Therefore, ensuring the accuracy of the ADC in the case of high-speed sampling is a critical issue. The performance of the ADC directly affects the performance of the entire system, and the performance test of the ADC becomes very important.
Current real-time signal processors require the ADC to be as close to the video, IF, and even RF as possible to obtain as much target information as possible. Therefore, the performance of the ADC directly affects the level and performance of the entire system, which makes the performance test of the ADC very important.
The performance test of the ADC chip is completed by the chip manufacturer, which requires the help of expensive semiconductor testing instruments, but for board-level and system-level designers, the more important thing is how to verify the chip’s performance in board-level or system-level applications real performance indicators.
The method of ADC static test has been studied for many years, and there are standard test methods in the world, but static test cannot reflect the dynamic characteristics of ADC, so it is necessary to carry out dynamic test.
2. The main parameters of ADC
The typical interface of ADC is shown in the figure below,
analog input section;
Programming control interface, such as SPI;
Sampling clock interface;
Power input interface.
ADC static indicators:
Differential nonlinear DNL
Integral nonlinear INL
Full Scale Gain Error
ADC dynamic indicators:
Total Harmonic Distortion THD
Signal-to-noise ratio and distortion SINAD
Effective number of bits ENOB
Spurious Free Dynamic Range SFDR
3. Challenges of ADC testing and R&S solutions
ADC test can be divided into static test and dynamic test. The method of static test has been studied for many years, and there are standard test methods in the world, but static test cannot reflect the dynamic characteristics of ADC, so it is necessary to carry out dynamic test.
The challenges are mainly divided into the following five points:
1. Power supply:
In order to ensure the normal operation of the system, a smooth voltage is required to power the ADC and clock. In today’s ADC designs, low dropout (LDO) regulators are often used to improve voltage stability.
Low power supply ripple noise and low voltage deviation are required.
2. Power Integrity:
Power integrity issues such as ripple noise and crosstalk can severely impact ADC performance.
The oscilloscope and probe are required to have high sensitivity, high offset and powerful FFT multi-domain measurement capability.
3. Clock Alternatives:
Clock performance is critical to the ADC.
Clock replacements requiring superior phase noise and jitter performance, high spectral purity, and high power
4. Clock verification:
Clock jitter and spectral purity directly affect the dynamic range of an ADC.
It is required that the phase noise analyzer has high sensitivity, can measure additional phase noise, and can perform spectrum measurement.
5. Performance characteristic test:
ADC performance parameters directly affect the overall performance of the system.
The test analyzer is required to have high spectral purity, outstanding bandwidth and EVM performance, high trigger accuracy, fast decoding function speed, and comprehensive jitter analysis functions.
In response to the above challenges, the test solutions and advantages provided by Rohde & Schwarz are as follows:
1. Power supply scheme:
Using the R&S?NGM, R&S?NGL and HMP series of high-performance/professional power supplies can deliver smooth, stable and precise DC power to the ADC. The advantages of this solution include:
Up to four isolated channels; high precision, high transient performance
Low Ripple Noise; Arbitrary Wave, High Sampling Data logger
2. Power Integrity Scheme:
Using R&S®RTO, RTE series oscilloscopes and RT-ZPR power rail probes to measure power integrity, the advantages of this solution include:
RT-ZPR probe 1:1 attenuation; 4GHz bandwidth; ultra-high sensitivity
High precision DC voltmeter; offset range ±60V
RTO, RTE oscilloscope; 16-bit resolution; capture rate of millions of waveforms per second
Hardware quasi-real-time FFT; simultaneous analysis in time domain and frequency domain
Scan the code to download R&S oscilloscope product solutions
3. Clock alternatives:
Using the R&S?SMA100B and R&S?SMB100A signal sources to provide clock replacements in different performance ranges, the advantages of this solution include:
SMA100B frequency 20GHz; best jitter/phase noise performance
Fully lossless Electronic attenuators; multiple options for different performance levels
R&S? SMB100A frequency 40GHz; excellent performance at ultra-low clock frequency
High output power; compensated losses; SMAB-B29 clock source secondary output
Scan the code to download R&S signal source product solutions
4. Clock verification scheme:
R&S offers an industry-leading portfolio of solutions for clock verification in all performance ranges:
Option 1: Use R&S?FSWP phase noise analyzer and VCO tester for clock verification;
Option 2: Clock verification using the R&S?FSW, R&S?FSVA, R&S?FSV and R&S?FPS spectrum analyzers and their phase noise measurements.
Advantages of this group of programs include:
Market-leading sensitivity to cross-correlated phase noise and jitter performance; ultrafast phase noise measurements
Characterization of random and periodic jitter; simultaneous AM and phase noise measurements
5. Performance characteristic test plan:
Using the R&S?SMA100B, R&S?SMBV100A and R&S?SMW200A for performance characterization testing, the advantages of this solution include:
SMA100B provides super pure analog input signal
SMBV100A or SMW200A provides modulation input with up to 2GHz bandwidth
4. ADC parameter test scheme
The traditional solution is to give an ideal analog signal to the ADC input port, an ideal sampling signal to the clock port, and corresponding accessories such as a DC power supply and a filter. Then collect and analyze the data after ADC conversion. The signal quality of the signal source exceeds that of the ADC under test. The performance test of ADC requires the cooperation of multiple high-performance analog signal sources and software to analyze the test results.
4.1 Test plan 1:
The test system includes four instruments: a signal source SMA100B is used to generate a high-precision and high-purity sine wave for the ADC to be tested as a source input, and the ADC is controlled by the sampling clock provided by another signal source SMA100B. This sine wave Sampling is performed, and the transformed result is acquired by software or the optional RTO oscilloscope logic analyzer.
The two SMA100B signal sources synchronize the reference frequency of 10MHz, so that the phase noise of the two signal sources is correlated within the loop bandwidth (1Hz-100Hz) and will not affect the test results.
The phase noise of the SMA100B signal source is extremely low, and the quality of the generated sine wave is extremely high. As shown in the SSB indicator in the figure below, the phase noise of the 1GHz frequency signal can be as low as -155dBc (10k offset).
The jitter of the clock has a great influence on the measurement results, and a low-jitter signal generator is required to generate the sampling clock of the ADC in the test. SMA100B is used as the source of the clock, and its jitter index is also quite excellent, which can be controlled at the fs level.
The digital results after ADC conversion are collected and analyzed by computer software or the logic analysis option of the oscilloscope. Usually the manufacturer provides an evaluation board for a certain ADC, and the USB interface on the evaluation board can transfer the results back to the computer software for analysis. If the oscilloscope logic analysis option is used, the option works in the state sampling mode, the number of channels to be used depends on the number of bits of the ADC, the state sampling rate depends on the sampling rate of the ADC, and the storage depth depends on the sampling rate and the frequency to be analyzed resolution.
4.2 Test plan 2:
If the application of ADC does not use down-sampling (IF digital down-conversion), the following solutions can be used to save costs. R&S’s analog signal source SMA100B is a single instrument that can provide analog signal output and sampling clock output at the same time, saving one signal source.
5. Analysis of typical results of ADC test
5.1 Input Signal Quality Test
Use an oscilloscope to perform FFT analysis on the input signal to understand the performance of the signal at different stages, including:
sources of interference, etc.
Advantages of RTO oscilloscopes:
High dynamic range, low noise
Hardware near real-time FFT
The measurement analysis is shown in the following figure:
5.2 Output signal quality test and analysis
Connect the ADC output to the digital input channel of the oscilloscope through the probe, configure the bus definition of each channel, measure and verify the correctness of the output data, and analyze the signal quality.
Advantages of RTO oscilloscope:
16 channels; up to 400MHz switching rate
5GSa/s sampling rate; 200Msa/CH storage
The analog bus shows “analog bus”
A screenshot of the settings is as follows:
Analyze the output signal quality with the Analog Bus Display. The traditional bus decoding is a combined bus display, which is a summary display of the data for a certain period of time. The RTO’s innovative analog bus display Analog bus displays the analog waveform represented by the bus data, making it easier to compare input and output signals. As shown below:
Analyze ADC output signal (analyzable by MATLAB): save analog bus waveform –> perform FFT and corresponding spectral measurements (FFT requires resampling to enhance timing accuracy) –> correlate input and output signals to test ADC performance.
Debug output signals. The analog bus display is helpful for finding signal distortions, as shown in the following figure:
5.3 Programming Interface Test
Use the digital channel of the oscilloscope to connect to the SPI interface, use the SPI protocol to decode, and set the trigger on the SPI “start of frame”. Measure the delay time from SPI command to ADC operation.
Advantages of RTO oscilloscopes:
Triggering and decoding for common low-speed serial buses
Time-dependent measurements of analog, digital, and bus decoding
The measurement results are as follows:
To sum up, in the face of the rapid development of ADC demand and ADC technology, Rohde & Schwarz provides you with optimal measurement instruments and solutions to help you obtain simple test procedures and accurate test results.
About Rohde & Schwarz
Rohde & Schwarz is an independent international technology company that develops, manufactures and markets innovative communications, information and security products for professional users. The company’s main business areas include test and measurement, broadcast television and media, aerospace | defense | security, network information security and cover many different industries and government market branches. As of June 30, 2019, Rohde & Schwarz employed approximately 12,000 people. The company is headquartered in Munich, Germany. Globally, the company has subsidiaries in more than 70 countries and regional centers in Asia and the United States.