Xilinx FPGAs Can Significantly Improve Beamforming System Designs
Beamforming is a signal processing technique that uses a series of sensors to achieve directionality, increase the strength of the transmitted signal, and improve the quality of the received signal. Beamforming is widely used in communications, radar, countermeasures, weapons systems, oil and mineral exploration, medical imaging, and direction finding.
In a direction finding application, we locate the angle of arrival of a signal source by steering a beamforming antenna. Two or more antenna arrays can be used to triangulate the exact location of the signal source, which is essential for large-scale signals intelligence and counterterrorism operations. The accuracy of this technique depends on the precise setting of gain and phase between the beamforming channels. We achieve fine tuning by using Pentek products built on Xilinx Virtex-6 FPGAs with native custom IP to improve system performance and accuracy.
We usually use beamforming techniques implemented by a series of sensors or antennas to improve reception performance in a specific direction (as shown in Figure 1 for a mobile phone in a certain direction). The signal from the signal source arrives at each antenna in turn according to the distance between the signal source and the antenna, so that there will be relative phase and amplitude shifts between the antenna signals.
Adjusting the gain and phase of each antenna signal during beamforming compensates for different delays in the signal path. Conditioning is done by synchronizing the signal from each antenna with the signal from a particular direction. When the signals are added, the non-directional signals from the other directions cancel each other out, while the signals from the beamforming direction add up beneficially, significantly improving the signal-to-noise ratio. In this tuning method, we effectively steer the antenna in the direction of the signal source by electronically adjusting the gain and phase on each path.
Eight channel system
In this system, we have arranged 8 antennas in a linear array, as shown in the overall block diagram in Figure 2. The antenna frequency here is 2.5GHz, so each antenna signal needs to be amplified, filtered, and then down-converted to an intermediate frequency (IF), so that the analog-to-digital converter can digitize the signal at a suitable sampling frequency. To maintain a fixed phase relationship for beamforming, all 8 channels must be sampled simultaneously.
We then downconvert the signal samples from each analog-to-digital converter to a complex I+Q signal at baseband in a digital downconverter (DDC), which also involves channel-specific phase and gain for beamforming “weights” adjust. Finally we add all eight baseband signals in the summation block to generate the beamformed summation signal. The CPU analyzes the summed signal and adjusts the phase and gain factors to track or adapt to the new target.
The FPGA has access to all data and control paths on the board, supporting factory-installed functions such as data multiplexing, channel selection, data packing, gating, triggering, and memory control. Each of these functions exists as an IP block.
PENTEK Model 53661 Beamforming Board
The Pentek model 53661 software-defined radio board is a 3U OpenVPX Cobalt development board shown in the simplified block diagram of Figure 3. It uses four 200MHz 16-bit analog-to-digital converters, a timing, clock synchronization unit and a Xilinx Virtex-6FPGA.
The FPGA has access to all data and control paths on the board, supporting factory-installed functions such as data multiplexing, channel selection, data packing, gating, triggering, and memory control. The Cobalt architecture builds the FPGA as a kind of container for data processing applications, where each function exists as an IP block.
We can use a variety of different FPGAs such as LX240T, LX365T, SX315T, and SX475T to implement the specific requirements of the processing task. With up to 2,016 DSP48Eslices, SXT devices are ideal for modulating/demodulating, encoding/decoding, encrypting/decrypting, and channelizing signals between transmit and receive.
The FPGA comes pre-installed with four DDC IP cores, each capable of receiving analog-to-digital samples from any of the four analog-to-digital converters. The decimation range of each DDC is 2K-64K, which can provide down-conversion baseband bandwidth of 2.5KHz-80MHz. Each DDC has programmable gain and phase shift controls, providing access to the processor across the entire VPX backplane. In this system we will assign an analog-to-digital converter to each DDC.
At each DDC output there is a power meter that calculates the power of the downconverted signal. Each power meter is equipped with a threshold detector to generate a system interrupt when the output power exceeds an upper threshold or falls below a lower threshold. These features greatly simplify gain calibration and signal monitoring, solving a problem that a system processor can only do in software.
In addition, the 53661 FPGA includes a local Aurora summation block that adds the four DDC outputs together to achieve the desired channel combination for beamforming. Aurora is a lightweight link layer gigabit serial protocol for Xilinx FPGAs. On this board, the Aurora interface receives the sum of incoming transfers on one input port over 4 serial links (4X) and delivers a new sum of transfers containing the contents of the 4 onboard channels on the 4X output port. Each 4X link operates at a clock bit rate of 3.125Gbps with data transfer rates up to 1.25GBps.
A native PCIe x4 interface IP running at a serial clock rate of 2.5Gbps provides a 1GBps link to the control processor for DDC and beamforming parameter programming. In addition, this PCIe link supports the delivery of 4 DDC outputs and beamforming summed outputs.
A programmable gigabit serial crossbar connects two 4X Aurora sum links and x4 PCIe links to the VPX P1 backplane connectors. This crossbar is highly flexible and enables the 53661 to operate in a variety of OpenVPX backplane topologies and slot configurations. In this system, we map the Aurora links to the OpenVPX extension plane. Likewise we can map the PCIe interface to the OpenVPX data plane which acts as the control plane.
Eight-Channel 3U OPENVPX Beamforming System
Figure 4 shows the complete eight-channel OpenVPX beamforming system. Two model 53661 development boards are installed in slot 1 and slot 2 of the OpenVPX backplane, and the CPU development board is installed in slot 3. The 8 dipole antennas suitable for receiving 2.5GHz signals include low noise amplifiers, local oscillators RF tuner feedback signals, including tuners, mixers, etc. The RF tuner converts the 2.5GHz antenna frequency signal down to 50MHz IF.
A 200MHz 16-bit analog-to-digital converter digitizes the IF signal and performs further downconversion to baseband, using a DDCS decimation of 128. This provides an I+Q complex output sample with a bandwidth of approximately 1.25MHz. The phase and gain coefficients of each channel are used to control the directivity of the array.
The CPU board in VPX slot 3 sends commands and coefficients across the backplane via two x4 PCIe links, also known as OpenVPX “thick pipes”.
We process the first 4 signal channels in the upper left part of the 53661 board in VPX slot 1, then the beamformed sums of these 4 channels are transmitted across the backplane to the 4X Aurora summing input port for the second 53661 development board. Then add the four-channel local sum of the second 53661 development board to the sum transmitted from the first development board to get the full eight-channel sum. This sum is sent to the CPU card in slot 3 via the x4 PCIe link.
The assignment of the 3 OpenVPX 4x links (OpenVPX thick pipes) on the Model 53661 board is simplified by using the crossbars in the previous block diagram. This allows the 53661 to operate with a variety of different backplanes. Since OpenVPX does not constrain the use of serial protocols across backplane links, the mixed protocol architecture supported by the system is shown in the figure.
Beamforming Demonstration System
Pentek engineers have built an eight-channel beamforming demonstration system with a control panel running on a CPU development board under Windows. An automatic signal scanner detects the strongest signal frequencies from the test transmitter. The center of this frequency is the 50MHz IF frequency of the RF downconverter. Once the frequency is found, the 8 DDCs are set accordingly, reducing the signal to 0Hz for easy summing. In addition, the control panel software enables specific hardware settings for all parameters of the 8 channels, including gain, phase and sync delay.
Another Display shows the beamforming pattern of the array. By adjusting the phase shift of the 8 channels, the sensitivity is maximized over the entire range of arrival angles from -90° to +90° perpendicular to the plane of the array to form the display content.
Compare the theoretical seven-lobe plot with the actual coordinate plot for an ideal eight-element array with a signal arrival angle of 0° (from directly in front of the array). Below the lobe plot is a polar plot showing a single vector pointing to the calculated angle of arrival. This vector is obtained by determining the lobe with the largest response.
Also shown is the actual coordinate diagram of the actual transmitter placed directly in front of the display as the source of the signal. In this case, the ideal lobe pattern is affected by physical objects, reflections, cable length variations, and antenna nuances. In any case, the computation of orientation information is ideal. As the signal source moves left and right in front of the array, the peak lobe moves with it, changing the calculated angle of arrival.
The demo system is now available online through Pentek. Readers who wish to see a live demo are invited to visit http://pentek.com/go/xcellbf.